With the integrated circuit industry are kept developing according to the Moore Law, feature sizes of CMOS devices are kept shrinking. Planar bulk silicon CMOS structure devices have encountered serious challenges. To solve these issues, various novel device structures have been developed. Among a number of novel device structures, a fin field effect transistor (FinFET) is one of the most promising novel device structures that will take the place of planar bulk silicon CMOS devices. The FinFET has become an international research focus.
In early days, a FinFET structure device is manufactured on an SOI substrate, and the process for manufacturing such a device is relatively simple as compared with that for manufacturing such a device on a bulk silicon substrate. However, there are several drawbacks for an SOI FinFET, such as high manufacturing cost, poor heat dissipation, floating body effects, poor compatibility with the CMOS processes, etc. To solve these issues in connection with the SOI FinFET, researchers begin to study how to manufacture a FinFET device with a bulk silicon substrate, referred to as Bulk Silicon FinFET. The Bulk Silicon FinFET can be applied in the products such as DRAM, SRAM, etc. However, the conventional Bulk Silicon FinFET devices have several drawbacks as compared with the SOI FinFET devices, for example: short channel effects (SCEs) cannot be suppressed as required; a leakage path may still be formed with the portion of a fin at the bottom of a channel, which results in a large leakage; and the impurity profile cannot be well controlled.
To overcome above-mentioned problems and to promote the application of the FinFET structure devices, further researches in this field shall be carried out, which are very important for the application of the FinFET structure devices and the development of the semiconductor industry.